简介
定义：
address translation is a mapping between the elements of an N- element virtual address space (VAS) and an M-element physical address space (PAS)
MAP: VAS → PAS ∪ ∅MAP(A) =A’ (if data at virtual addr. A are present at physical addr. A_ in PAS)
MAP(A) = ∅ (if data at virtual addr. A are not present in physical memory)使用页表的地址翻译图
Figure 9.12 shows how the MMU uses the page table to perform this mapping. A control register in the CPU, the page table base register (PTBR) points to the current page table. The n-bit virtual address has two components: a p-bit virtual page offset (VPO) and an (n − p)-bit virtual page number (VPN). The MMU uses the VPN to select the appropriate PTE. For example, VPN 0 selects PTE 0, VPN 1 selects PTE 1, and so on. The corresponding physical address is the concatenation of the physical page number (PPN) from the page table entry and the VPO from the virtual address. Notice that since the physical and virtual pages are both P bytes, the physical page offset (PPO) is identical to the VPO.
页面命中
Figure 9.13(a) shows the steps that the CPU hardware performs when there is a page hit.
(注：VA——虚拟地址，PTEA——页表条目地址，PTE——页表条目，PA——物理地址)
Step 1. The processor generates a virtual address and sends it to the MMU.
Step 2. The MMU generates the PTE address and requests it from the cache/main memory.
Step 3. The cache/main memory returns the PTE to the MMU.
Step 4. The MMU constructs the physical address and sends it to the cache/main memory.
Step 5. The cache/main memory returns the requested data word to the pro-cessor.页面不命中
Unlike a page hit, which is handled entirely by hardware, handling a page fault requires cooperation between hardware and the operating system kernel (Figure 9.13(b)).
Steps 1 to 3. The same as steps 1 to 3 in Figure 9.13(a).
Step 4. The valid bit in the PTE is zero, so the MMU triggers an exception,which transfers control in the CPU to a page fault exception handler in the operating system kernel.
Step 5. The fault handler identifies a victim page in physical memory, and if that page has been modified, pages it out to disk.
Step 6. The fault handler pages in the new page and updates the PTE in memory.
Step 7. The fault handler returns to the original process, causing the faulting instruction to be restarted. The CPU resends the offending virtual address to the MMU. Because the virtual page is now cached in physical memory, there is a hit, and after the MMU performs the steps in Figure 9.13(a), the main memory returns the requested word to the processor.